View SM5876_157890.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SM5876AM
NIPPON PRECISION CIRCUITS INC.
3rd-order , 2-channel D/A Converter
OVERVIEW
The SM5876AM is a 3rd-order , 2-channel D/A converter LSI for CD-ROM digital audio reproduction equipment. It incorporates an 8-times oversampling digital filter, deemphasis filter, attenuator, and soft mute circuits built-in., using NPC's Molybdenum-gate CMOS technology. The SM5876AM operates from a 2.7 to 5.5 V supply, and is available in 24-pin SSOPs.
PINOUT
MLEN CKSL CKO DVSS BCKI DI DVDD LRCI TSTN LO AVDDL LON
1 24
FEATURES
s
s s s
s
s
s s
s
s
s s
s s
System clock * 768fs (33.8688MHz) * 384fs (16.9344MHz) Crystal oscillator circuit built-in Infinity-zero detector circuit built-in MSB first, rear-packed serial data input format ( 64fs bit clock) 8-times oversampling digital filter * 32 dB stopband attenuation * 0.05 dB passband ripple * -0.34 dB passband correction for 70 kHz LPF 3-line microcontroller interface for output mode and attenuator control settings 16 output modes Deemphasis filter operation * 36 dB stopband attenuation * -0.09 to +0.23 dB deviation * -0.34 dB passband correction for 70 kHz LPF Attenuator * 8-bit attenuator (linear 256 steps) * Independent left/right-channel set function * Soft mute function (approx. 1024/fs mute time) 2-channel D/A converter * 3rd-order noise shaper * 32fs oversampling 44.1 kHz sampling frequency 2.7 to 5.5 V operating supply voltage range (4.5 to 5.5 V operating supply voltage range with 768fs system clock) 24-pin SSOP Molybdenum-gate CMOS process
12
13
MCK MDT RSTN MUTEO XVSS XTO XTI XVDD RO AVDDR RON AVSS
PACKAGE DIMENSIONS
Unit: mm
S M5 8 7 6 AM
24-pin SSOP
5.40 0.20 7.80 0.30
10.05 0.20 10.20 0.30 1.80 0.10
0.15 - 0.05
+ 0.1
0.10 0.10 2.10MAX
0.7
0.8
0.36 0.10
0.50 0.20
0 10
NIPPON PRECISION CIRCUITS--1
SM5876AM
BLOCK DIAGRAM
LRCI BCKI DI
Input interface
MLEN MCK MDT L R
MUTEO
Microcontroller interface
Filter & attenuation operation block
L R CKO XVSS XTO
RSTN CKSL DVSS DVDD TSTN
Timing control
L
PWM data generation block
R
Noise shaper operation block
XTI
XVDD
AVDDL
AVDDR
LO
LON
AVSS
RON
RO
PIN DESCRIPTION
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name MLEN CKSL CKO DVSS BCKI DI DVDD LRCI TSTN LO AVDDL LON AVSS RON O O Ip Ip O Ip Ip I/O Ip Ip O Microcontroller control latch clock input 768fs/384fs clock select. 768fs when HIGH, and 384fs when LOW. Oscillator clock buffer output Digital ground pin Data bit clock input pin Serial data input pin Digital supply pin Sample data rate (fs) clock input pin. Left channel when HIGH, and right channel when LOW. Test input pin Left-channel analog output (+) Left-channel analog supply pin Left-channel analog output (-) Analog ground pin Right-channel analog output (-) Description
NIPPON PRECISION CIRCUITS--2
SM5876AM
Number 15 16 17 18 19 20 21 22 23 24 Name AVDDR RO XVDD XTI XTO XVSS MUTEO RSTN MDT MCK O Ip Ip Ip I O O I/O Right-channel analog supply pin Right-channel analog output (+) Crystal oscillator supply pin Crystal oscillator or external clock input pin Crystal oscillator output pin Crystal oscillator ground pin Infinity-zero detector output (analog mute control) Reset pin. Reset when LOW. Microcontroller control data input pin Microcontroller control clock input pin Description
I: INPUT O: OUTPUT Ip: Input with pull-up Registor
SPECIFICATIONS
Absolute Maximum Ratings
DVSS = AVSS = XVSS = 0 V, AVDD = AVDDL = AVDDR
Parameter Supply voltage range Input voltage range1 XTI input voltage range Storage temperature range Power dissipation Soldering temperature Soldering time 1. Pins MLEN, CKSL, BCKI, DI, LRCI, TSTN, MCK, MDT. Also applicable during supply switching. Symbol DV DD, AV DD, XVDD V IN1 V IN Tstg PD Tsld tsld Rating -0.3 to 7.0 DV SS - 0.3 to DV DD + 0.3 XV SS - 0.3 to XVDD + 0.3 -40 to 125 250 255 10 Unit V V V C mW C s
Recommended Operating Conditions
5 V operation: DVSS = AVSS = XVSS = 0 V, AVDD = AVDDL = AVDDR
Parameter Supply voltage range Symbol DV DD, AV DD, XVDD DV DD - XVDD, DV DD - AV DD, XV DD - AV DD, DV SS - XVSS, DV SS - AV SS, XV SS - AV SS Topr Rating 4.5 to 5.5 Unit V
Supply voltage variation
0.1
V
Operating temperature range
-40 to 85
C
NIPPON PRECISION CIRCUITS--3
SM5876AM 3 V operation: DVSS = AVSS = XVSS = 0 V, AVDD = AVDDL = AVDDR, CKSL = LOW (384fs)
Parameter Supply voltage range Symbol DV DD, AV DD, XVDD DV DD - XVDD, DV DD - AV DD, XV DD - AV DD, DV SS - XVSS, DV SS - AV SS, XV SS - AV SS Topr Rating 2.7 to 4.5 Unit V
Supply voltage variation
0.1
V
Operating temperature range
-20 to 70
C
DC Electrical Characteristics
5 V operation: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 4.5 to 5.5 V, AVDD = AVDDL = AVDDR, Ta = -40 to 85 C
Rating Parameter DVDD digital supply current1 XVDD system clock supply current1 Symbol IDDD IDDX IDDA V IH1 V IL1 V INAC V IH2 V IL2 VOHA VOLA VOHC VOLC IIH1 IIL1 IIL2 ILH IOH = -1 mA IOL = 1 mA IOH = -1 mA IOL = 1 mA V IN = XVDD V IN = 0 V V IN = 0 V V IN = DV DD Total current Clock input Clock input Condition min - - - 0.7XVDD - 0.3XVDD 2.4 - AV DD - 0.4 - DV DD - 0.4 - - - - - typ 15 6 1 - - - - - - - - - 12 12 12 - max 25 10 2 - 0.3XVDD - - 0.5 - 0.4 - 0.4 25 25 25 1.0 mA mA mA V V V p-p V V V V V V A A A A Unit
AVDD analog supply current1 XTI HIGH-level input voltage XTI LOW-level input voltage XTI AC-coupled input voltage HIGH-level input voltage2 LOW-level input voltage2 HIGH-level output voltage3 LOW-level output voltage3 CKO HIGH-level output voltage CKO LOW-level output voltage XTI HIGH-level input current XTI LOW-level input current LOW-level input current2 Input leakage current2
1. DV DD = AV DD = XVDD = 5 V, CKSL = HIGH (768fs), XTI clock input frequency fXTI = 33.8688 MHz, no output load, NPC-standard input data pattern. 2. Pins MLEN, CKSL, BCKI, DI, LRCI, TSTN, MCK, MDT. 3. Pins LO, LON, RO, RON,MUTEO.
3 V operation: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 2.7 to 4.5 V, AVDD = AVDDL = AVDDR, Ta = -20 to 70 C
Rating Parameter DVDD digital supply current1 XVDD system clock supply current1 Symbol IDDD IDDX IDDA V IH1 Total current Clock input Condition min - - - 0.7XVDD typ 6 1.5 0.5 - max 9 3 1 - mA mA mA V Unit
AVDD analog supply current1 XTI HIGH-level input voltage
NIPPON PRECISION CIRCUITS--4
SM5876AM
Rating Parameter XTI LOW-level input voltage XTI AC-coupled input voltage HIGH-level input voltage2 LOW-level input voltage2 HIGH-level output voltage3 LOW-level output voltage3 CKO HIGH-level output voltage CKO LOW-level output voltage XTI HIGH-level input current XTI LOW-level input current LOW-level input current2 Input leakage current2 Symbol V IL1 V INAC V IH2 V IL2 VOHA VOLA VOHC VOLC IIH1 IIL1 IIL2 ILH IOH = -0.5 mA IOL = 0.5 mA IOH = -0.5 mA IOL = 0.5 mA V IN = XVDD V IN = 0 V V IN = 0 V V IN = DV DD Condition min Clock input - 0.3XVDD 2.4 - AV DD - 0.4 - DV DD - 0.4 - - - - - typ - - - - - - - - 4 4 4 - max 0.3XVDD - - 0.5 - 0.4 - 0.4 15 15 15 1.0 V V p-p V V V V V V A A A A Unit
1. DV DD = AV DD = XVDD = 3 V, CKSL = LOW (384fs), XTI clock input frequency fXTI = 16.9344 MHz, no output load, NPC-standard input data pattern. 2. Pins MLEN, CKSL, BCKI, DI, LRCI, TSTN, MCK, MDT. 3. Pins LO, LON, RO, RON,MUTEO.
AC Electrical Characteristics
5 V operation: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 4.5 to 5.5 V, AVDD = AVDDL = AVDDR, Ta = -40 to 85 C 3 V operation: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 2.7 to 4.5 V, AVDD = AVDDL = AVDDR, Ta = -20 to 70 C, CKSL = LOW (384fs system clock) System clock (XTI)
Crystal Oscillator
Rating Parameter Symbol Condition min 768fs Oscillator frequency fOSC 384fs 8.0 4.0 typ 33.8688 16.9344 max 35.6 17.8 MHz MHz Unit
External clock input
Rating Parameter Symbol Condition min 768fs HIGH-level clock pulsewidth tCWH 384fs 768fs LOW-level clock pulsewidth tCWL 384fs 768fs Clock pulse cycle tXI 384fs 13.0 26.0 13.0 26.0 28.0 56.0 typ 14.75 29.5 14.75 29.5 29.5 59.0 max 62.5 125 62.5 125 125 250 ns ns ns ns ns ns Unit
NIPPON PRECISION CIRCUITS--5
SM5876AM
XTI input clock
t CWH t XI
Serial input (BCKI, DI, LRCI)
t CWL
VIH1 0.5VDD VIL1
Rating Parameter BCKI HIGH-level pulsewidth BCKI LOW-level pulsewidth BCKI pulse cycle DI setup time DI hold time Last BCKI rising edge to LRCI edge LRCI edge to first BCKI rising edge Symbol min tBCWH tBCWL tBCY tDS tDH tBL tLB 50 50 1/(64fs) 50 50 50 50 typ - - - - - - - max - - - - - - - ns ns ns ns ns ns ns Unit
Serial input timing
t BCWH BCKI t DS DI t BL LRCI t DH
t BCY
t BCWL 1.5V
1.5V t LB 1.5V
NIPPON PRECISION CIRCUITS--6
SM5876AM Control input (MCK, MDT, MLEN)
Rating Parameter MCK HIGH-level pulsewidth MCK LOW-level pulsewidth MCK pulse cycle MDT setup time MDT hold time MLEN setup time MLEN hold time MLEN level pulsewidth Rise time Fall time Symbol min tMCWH tMCWL tMCY tMDS tMDH tMLS tMLH T MLH tr tf 140 140 280 100 100 1/(192fs) + 20 1/(192fs) + 20 1/(192fs) + 20 - - typ - - - - - - - - - - max - - - - - - - - 50 50 ns ns ns ns ns ns ns ns ns ns Unit
Control input timing
MCK tMCWH tMCY MDT tMDH tMLS MLEN tMLY tf MCK MDT MLEN
Reset Input (RSTN)
Rating Parameter RSTN LOW-level pulsewidth after supply rising edge Symbol min tRSTN 50 typ - max -
2.4V 0.5V 0.5V
1.5V tMCWL
1.5V tMDS tMLH 1.5V
tr
2.4V
1.5V
Unit ns
NIPPON PRECISION CIRCUITS--7
SM5876AM
Theoretical Filter Characteristics
Deemphasis OFF overall characteristics
Frequency band Parameter f Passband ripple Stopband attenuation Built-in analog LPF compensation 0 to 0.4535fs 0.5465fs to 7.4535fs 0.4535fs @ fs = 44.1 kHz 0 to 20.0 kHz 24.1 to 328.7 kHz 20.0 kHz min -0.05 32 - typ - - -0.34 max +0.05 - - Attenuation (dB)
Overall frequency characteristic (deemphasis OFF)
0
10
20
Gain (dB)
30
40
50
60 0.0
1.0
2.0
3.0
4.0 Frequency (fs)
5.0
6.0
7.0
8.0
Passband characteristic (deemphasis OFF)
0.0
0.2 Gain (dB)
0.4
0.6 0.8 0.000
0.125
0.250 Frequency (fs)
0.375
0.4535
0.500
NIPPON PRECISION CIRCUITS--8
SM5876AM Deemphasis ON overall characteristics
Frequency band Parameter f Deviation from ideal deemphasis filter characteristics Stopband attenuation Built-in analog LPF compensation 0 to 0.4535fs 0.5465fs to 7.4535fs 0.4535fs @ fs = 44.1 kHz 0 to 20.0 kHz 24.1 to 328.7 kHz 20.0 kHz min -0.09 36 - typ - - -0.34 max +0.23 - - Attenuation (dB)
Overall frequency characteristic (deemphasis ON)
0
10
20
Gain (dB)
30
40
50
60 0.0
1.0
2.0
3.0
4.0 Frequency (fs)
5.0
6.0
7.0
8.0
Passband characteristic (deemphasis ON)
0
2
4
Gain (dB)
6
8
10
12 0.000
0.125
0.250 Frequency (fs)
0.375
0.4535 0.500
NIPPON PRECISION CIRCUITS--9
SM5876AM
AC Analog Characteristics
5 V operation: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 5 V, AVDD = AVDDL = AVDDR, CKSL = 0 V, deemphasis OFF, crystal oscillator frequency fOSC = 16.9344 MHz, Ta = 25 C
Rating Parameter Total harmonic distortion LSI output level1 Evaluation board output level Dynamic range Signal-to-noise ratio2 Channel separation Symbol THD + N Vout1 Vout2 D.R S/N Ch. Sep Condition min 1 kHz, 0 dB 1 kHz, 0 dB 1 kHz, 0 dB 1 kHz, -60 dB 1 kHz, 0/- dB 1 kHz, -/0 dB - - 1.8 88 88 84 typ 0.005 1.53 2.0 92 92 86 max 0.01 - 2.2 - - - % V rms V rms dB dB dB Unit
1. The LSI output level = 0.3058AV DD Vrms. 2. Signal-to-noise is measured following a device reset, with DATA = 0 (DI = LOW). Under these conditions, the signal-to-noise ratio includes noise-shaper noise.
3 V operation: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 3 V, AVDD = AVDDL = AVDDR, CKSL = 0 V, deemphasis OFF, crystal oscillator frequency fOSC = 16.9344 MHz, Ta = 25 C
Rating Parameter Total harmonic distortion LSI output level1 Evaluation board output level Dynamic range Signal-to-noise ratio2 Channel separation Symbol THD + N Vout1 Vout2 D.R S/N Ch. Sep Condition min 1 kHz, 0 dB 1 kHz, 0 dB 1 kHz, 0 dB 1 kHz, -60 dB 1 kHz, 0/- dB 1 kHz, -/0 dB - - - - - - typ 0.007 0.92 1.2 90 90 82 max - - - - - - % V rms V rms dB dB dB Unit
1. The LSI output level = 0.3058AV DD Vrms. 2. Signal-to-noise is measured following a device reset, with DATA = 0 (DI = LOW). Under these conditions, the signal-to-noise ratio includes noise-shaper noise.
NIPPON PRECISION CIRCUITS--10
SM5876AM
AC Measurement Circuit and Conditions
Measurement circuit block diagram
CKO (768fs/384fs)
Signal Generator
BCK LRCK(fs) DATA
Left Channel
Evaluation L/R Channel Board Selector Right Channel
Distortion Analyzer
fs= 44.1kHz DATA= 16bit
10k Input Impedance NF Corporation 3346A
RMS Measurement Shibasoku AD725C
Measurement conditions
Parameter1 Total harmonic distortion Output level Dynamic range Signal-to-noise ratio Symbol THD + N Vout DR S/N D-RANGE THRU 20 kHz lowpass filter ON 400 Hz highpass filter OFF JIS A filter ON 20 kHz lowpass filter ON 400 Hz highpass filter OFF 3346A left/right-channel selector switch THRU AD725C distortion analyzer with built-in filter 20 kHz lowpass filter ON 400 Hz highpass filter OFF
Channel separation
Ch. Sep
THRU
1. Pins LO and RO should have an output load of 10 k (min).
NIPPON PRECISION CIRCUITS--11
XVDD 0.01 100 0.01 10 10 + + VCC AGND VEE X'tal AVDD 10p 0.1 10k 100 24k - + 680p U3 NJM5532 1/2 15k 22k 2.2 100k - + 24k
AVSS
+
0.01 0.01 0.01 10p 0.01 10 10 + +
Measurement circuit
XVSS
AVSS 8.2k 100p + 100p
15k
220p 10k 0.1 + 100 8.2k U3 NJM5532 1/2 100p
100 R OUTPUT
MCK MDT RSTN
MUTEO XVSS XTO XTI XVDD RO AVDDR RON
SM5876AM
SM5876
15k 10k 8.2k 24k - 8.2k + 24k + 100 220p 10k 0.1 0.1 100 15k 22k - 680p + U4 NJM5532 1/2 100k + 100p 100p 2.2 100 L OUTPUT
TSTN LO AVDDL LON
MLEN CKSL CKO DVSS
MUTEO CKO MDT MCK LRCI BCKI DI MLEN CKSL RSTN U4 NJM5532 1/2 100p
J1
BCKI DI DVDD LRCI
+ 0.01 220 DVDD DVSS
NIPPON PRECISION CIRCUITS--12
SW3
SW4
SM5876AM
FUNCTIONAL DESCRIPTION
System Clock/Speed Switching (XTI, XTO, CKO, CKSL)
The system clock on XTI can be set to run at one of two speeds, 384fs (normal speed) or 768fs (doublespeed), where fs is the input frequency on LRCI. The speed for CD playback is set by the input level on CKSL, as shown in table 1.
Table 1. System clock select
CKSL Parameter XTI input clock frequency CD playback XTI frequency CKO output clock frequency Internal system clock period Symbol HIGH fXI (= 1/tXI) fXI 768fs 33.8688 MHz at fs = 44.1 kHz 768fs LOW 384fs 16.9344 MHz at fs = 44.1 kHz 384fs
Note that the input clock accuracy and signal-tonoise ratio greatly influence the AC analog characteristics. Accordingly, care should be taken to ensure that the clock is free from jitter. The system clock can be controlled by a crystal oscillator comprising a crystal connected between XTI and XTO and the built-in CMOS inverter. Alternatively, an external system clock can be input on XTI. As the internal CMOS inverter has a feedback resistor, the external clock can be AC coupled to XTI. The system clock is output on CKO.
fCO TSYS
2tXI
tXI
System Reset (RSTN)
The device should be reset in the following cases.
s s
s
At power ON When LRCI and/or the system clock XTI stop, or other abnormalities occur. When switching the XTI clock 768fs 384fs.
The device is reset by applying a LOW-level pulse on RSTN. At system reset, the internal arithmetic operation and output timing counter are synchronized on the next LRCI rising edge, as shown in figure 1.
RSTN LRCI
Internal Reset
Low 1 2 3 9 10
LO(LON) RO(RON)
Output Muted
Figure 1. System reset timing Output mute At power-ON reset (when RSTN goes LOW), the outputs LO (LON) and RO (RON) enter the output mute state. Mute is released on the 9th LRCI rising edge after RSTN goes HIGH. During this cycle, the timing reset can cause output noise to be generated.
NIPPON PRECISION CIRCUITS--13
SM5876AM
Infinity-Zero Detector (analog mute control) Output (MUTEO)
The SM5876AM outputs an infinity-zero detection output signal under the following circumstances. 1. When an infinity-zero occurs on both the left and right channels. 2. When an infinity-zero occurs in the input data for the channel set by the output mode setting. 3. When the output mode setting is muting for both the left and right channels. 4. When the attenuation counter for both the left and right channels is 0 (-). Also from immediately after a reset input on RSTN until the initialization cycle finishes and the first data cycle occurs. In cases 1 and 2, from when an infinity-zero is detected a period of 214 x (1/fs) 0.37 seconds takes place before MUTEO goes HIGH. In cases 3 and 4, from when the attenuation counter value is 0 a period of 214 x (1/fs) 0.37 seconds takes place before MUTEO goes HIGH.
214/fs
1 2 3 8 9
LRCI DI RSTN MUTEO
Initialize Signal No Signal Signal
Figure 2. MUTEO output timing
Audio Data Input (DI, BCKI, LRCI)
The digital audio data is input on DI in MSB-first, 2s-complement, 16-bit serial format. Serial data bits are read into the SIPO register (serialto-parallel converter register) on the rising edge of the bit clock BCKI. The arithmetic operation and output timing are independent of the input timing. Accordingly, after a reset, as long as the clock frequency ratio between LRCI and the system clock XTI is maintained, phase differences between LRCI, BCKI and the system clock XTI do not affect the functional operation. Also, any jitter present on the data input clock does not appear as output pulse jitter. The bit clock frequency on BCKI should be between 32fs and 64fs. MDT, can control the left and right channels either independently or together (independent when the MDT attenuation control flag is LOW, and together when HIGH). The left-channel counter contents DATTL and the right-channel counter contents DATTR control the left-channel gain and right-channel gain, respectively, using the following equations. DATTL Left-channel gain = 20 x log ------------------ [dB] 255 DATTR Right-channel gain = 20 x log ------------------- [dB] 255 After system reset initialization, independent left/right-channel attenuation mode with the maximum gain of 0 dB is the default. Deemphasis filter (MDT DEM flag) The built-in digital deemphasis filter is designed to operate at 44.1 kHz. Deemphasis is ON when the DEM flag is HIGH, and OFF when the DEM flag is LOW. After reset, deemphasis OFF is the default.
Operating Modes (MLEN, MDT, MCK)
The microcontroller data is used to control the following parameters. Digital attenuator Digital attenuation is controlled by attenuation data input on MDT. The attenuation operation is determined by a mathematical operation of the internal 8-bit up/down counter's output data on the signal data. The 8-bit up/down counter, when attenuation data is input on
NIPPON PRECISION CIRCUITS--14
SM5876AM Output mode setting (MDT 4-bit data) The left-channel and right-channel outputs can be set to any one of 16 different modes, as shown in table 2.
Table 2. Output mode control
PL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PL1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PL2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PL3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Left-channel output Mute Mute Mute Mute R R R R L L L L (L + R)/2 (L + R)/2 (L + R)/2 (L + R)/2 Right-channel output Mute R L (L + R)/2 Mute R L (L + R)/2 Mute R L (L + R)/2 Mute R L (L + R)/2 Stereo Reverse Notes Mute
"Stereo" is the default after system reset. "Mute" refers to soft muting.
Soft mute (output mode setting) The channel output muting set by the output mode control 4-bit data is soft mute mode. The attenuation counter output decrements by 1 step at a time, reducing the gain. The signal is completely muted after a time of (1024/fs), which corresponds to approximately 23.2 ms when fs = 44.1 kHz. Conversely, when soft mute is released using the output mode control, the attenuation counter output increments by 1 step at a time, increasing the gain. The time taken to return to 0 dB from full muting is also (1024/fs). When an attenuation value is set, the output gain decreases from the value set by the attenuation data until the gain is -. Similarly for mute release, the output gain increases from the current value until the gain is 0 dB. Soft mute operation is shown in figure 3. Upon system reset initialization, mute is released, which corresponds to the maximum gain of 0 dB.
MUTE
0 dB Gain - 1024/fs 1024/fs
Figure 3. Soft mute operation example Attenuator control (ATC flag) The attenuator control (ATC) flag is input on MDT. When the ATC flag is HIGH, the left-channel and right-channel attenuator data is common. In this mode, the left-channel data is used for both channels.
NIPPON PRECISION CIRCUITS--15
SM5876AM
TIMING DIAGRAMS
Input Timing
(DI, BCKI, LRCI)
1/fs Left Channel 16 bit
MSB LSB
Right Channel
MSB
16 bit
LSB
DI BCKI
(64fs MAX)
LRCI
(MDT, MCK, MLEN)
L channel Attenuation Data R channel Attenuation Data Output Mode Control
MCK
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
PL0
6
PL1
5
PL2
4
3
2
1
0
MDATA
LSB MSB LSB MSB
PL3 DEM ATC
MLEN
Data is recognized on the rising edge of MLEN.
NIPPON PRECISION CIRCUITS--16
SM5876AM
TYPICAL APPLICATIONS
Input Interface Circuit
X'tal
XTI CKO 44.1kHz 2.1168MHz LRCI DI BCKI
XTO
SM5876
Note that the output analog characteristics and other specifications are not guaranteed for a particular format or application circuit.
Output Analog Processing Circuit
(Left channel only is shown.)
LON SM5876 LO
-
LOUT
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, 2-chome Fukuzumi Koutou-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9504BE 1996.06
NIPPON PRECISION CIRCUITS INC.
+
NIPPON PRECISION CIRCUITS--17

▲Up To Search▲

Price & Availability of SM5876

	To Download SM5876 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .